Fast and low-power circuit techniques suitable for size-configurable SRAM macrocells are described. An SRAM cell architecture using virtual-GND lines along bitlines is proposed; each virtual-GND line switches the potential by inner read-enable and column-address-decoded signals. Reducing the active power dissipation in the memory array and shortening the time for writing data are simultaneously accomplished. The range of available supply voltages is enhanced by adoptive higher virtual-GND level control with a simple voltage limiter. An SRAM-macrocell test chip is designed and fabricated with 0.5-µm CMOS technology. A 4K-word6-bit organization SRAM demonstrates 186-MHz operation at a 3.3-V typical power supply. Its power dissipation at a practical operating frequency, 100-MHz, is reduced to 29% (25-mW) by the proposed virtual-GND line techniques.

After analyzing the limitations of the traditional description of CMOS circuits at the gate level, this paper introduces the notions of switching and signal variables for describing the switching states of MOS transistors and signals in CMOS circuits, respectively. Two connection operations for describing the interaction between MOS transistors and signals and a new description for MOS circuits at the switch level are presented. This new description can be used to express the functional relationship between inputs and the output at the switch level. It can also be used to describe the circuit structure composed of MOS switches. The new description can be effectively used to design both CMOS circuits and nMOS pass transistor circuits.

Currently, a typical 5454 bit multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea in the present paper is a power optimization for the data compressors based on a Window Detector. The role of the Window Detector is detecting the input data, activating a selected operation unit, choosing the optimized output data, and driving the next stage. It can reduce the power consumption drastically because only one selected operation unit (a Window) is activated. The power consumption of the proposed data compressors is reduced by about 33%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one. Furthermore, the power consumption dependent on the input data transition is shown for both the static CMOS logic and the nMOS pass transistor logic.

The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.

To realize the high speed and low power CMOS Phase Locked Loop, we have developed new components of PLL: VCO and PFD. In the VCO, high speed and low power is realized with source coupled inverter pairs in the single loop three gate ring oscillator. And in the PFD, low power and small chip area are realized with the dynamic inverter. And with the simple design adjustment, both reduction of dead zone and immunity of current fluctuation at "O" output are implemented in Charge Pump. A fully CMOS PLL with these components have been designed with 0.8µ CMOS. At 622MHz operation, the power dissipation of 18mW is achieved by SPICE simulation.

This letter describes our DFB-LD module for use in WDM optical access networks. We realized an isolator-free DFB-LD module with a thermo-electric cooler in aim of stabilizing the emission wavelength for WDM systems. Silicon waferboard technology was employed to achieve simple assembly and small size of the module. This small size contributed to low TEC power. Our fabricated module demonstrated low-noise and stable emission wavelength characteristics under 156 Mbit/s pseudo random modulation.

In this paper, in order to achieve the low power consumption of programmable divider in a PLL frequency synthesizer, we propose a new prescaler method for low power consumption. A fixed prescaler is inserted in front of the (N +1/2) programmable divider which is designed based on the new principle. The divider ratio in the loop does not vary at all even if such a prescaler is utilized. Then the permissible delay periods of a programmable divider can be extended to two times as long as the conventional method, and the low power consumption and low cost in a PLL frequency synthesizer have been achieved.

In this paper, we discuss on accuracy of power dissipation medels for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods for CMOS circuits. However, we do not know how accurate they are because we have not established a method to compare the estimated results of power consumption with power consumption of actual VLSI chips. To evaluate the accuracy of several kinds of power dissipation models in chip-level, block-level and gate-lebel etc., we have been (i) Measuring power consumtion of actual microprocessors, (ii) Estimating power consumption with several kinds of power dissipation models, and (iii) Comparing (i) with (ii). The experimental results show as follows: (1) Power estimation at gate level is accurate enough. (2) Estimating power of a clock tree independently makes estimation more accurate. (3) Area of each functional block is a good approximation of load capacitance of the block.

For low-voltage, high-speed operation of LSIs, the most attractive features in fully-depleted (FD) SOI devices are their steep subthreshold slope and reduced drain junction capacitance. This paper discusses the impact of these features on circuit performance. FD SOI devices can have a threshold voltage of more than 100 mV lower than that of bulk devices within the limits of acceptable off-state leakage current. Thus they hold higher driving current even at supply voltages of less than 1 V. On the other hand, the reduced junction capacitance is effective to suppress the total parasitic capacitance especially in lightly loaded CMOS circuits. These attractive features improve the speed performance in FD SOI circuits remarkably at supply voltages of less than 1 V. For high-speed circuit applications, 0.25-µm-gate SIMOX circuits, such as frequency dividers, prescalers, MUX, and DEMUX, can operate at up to 1-2 GHz even at a supply voltage of 1 V. CMOS/SIMOX logic LSIs also exhibit better performance at very low supply voltages. At merely 1 V, a SIMOX logic LSI could be functional at up to 60-90 MHz using 0.26-0.34 µW/MHz/Gate of power dissipation. Furthermore, SIMOX logic LSIs will allow 20-30 MHz operation at 0.5 V of a solar cell with reasonable chip size. These investigations lead to the conclusion that FD CMOS/SIMOX technology will have a large impact on the development of low-voltage high-performance LSIs for portable digital equipment and telecommunication systems.

A low power dual modulus prescaler for frequency synthesizers has been designed in a standard 1.2 µm digital CMOS process using enhancement source coupled logic (ESCL). Being a differential low amplitude current mode logic, ESCL has two interesting characteristics for this design besides low power consumption: the low noise performance, that allows this circuit to be on the same chip with sensitive analog circuitry, and the ability to run with a 200 mV sinusoidal signal as generated from an LC oscillator without the need of a clock amplifier. At 195 MHz and 3 V supply, the current consumption of the prescaler is as low as 289 µA, while maximum operating frequencies of 910 MHz at 5 V and 650 MHz at 3 V are achieved.

We have designed a new current-mode low-voltage, low-power, high-frequency CMOS VCO circuit. The main purpose of this new circuit is to obtain operational capabilities with more than 1 GHz oscillation frequency from one battery cell. The current-mode approach was adopted throughout the circuit design to achieve this. New differential-type delay cells in the current-mode operation enable extremely low supply voltage operation and superior linearity between the oscillation frequency and control voltage of a ring oscillator. A design which combines the transitions of each delay cell output enables the VCO's high-frequency operation. To obtain a sufficient current level at output, a current amplifier with a small amount of positive feedback is used. The unnecessary generation of spectral components caused by mismatched time delay of delay cells in a ring-oscillator, which is an inherent problem of the VCO in a ring-oscillator form, is 0also analyzed. The characteristics of the designed VCO were examined by the SPICE circuit simulation using standard CMOS 0.6µm devices. Operation with a 1 V power supply, 1 GHz oscillation frequency, and 5.7 mW power dissipation was verified.

This study proposes an amplitude limiting type spread spectrum communication to be applied to extremely low power radio wave communicaion and evaluates capability of the code division multiplex. First, changes in output from the correlation device, maximum power, and in allowable noise power are compared by computer simulation for the case where the number of multiplex channels is increased. Second, possible relationship between noise intensity and error rate is measured by actual loading experiments using a device developed for trial purpose. Third, majority decision logic is proposed for the said device to realize amplitude limiting type code division multiplex easily. When the amplitude is limited, the maximum power can be controlled at about 2 dB, and channels with more than half of the number of spread sign can be used. It is revealed that, in the spread spectrum, alteration of the number of multiplex channels is made easy by application of this method.

A low power consumption 16-bit fixed point Digital Signal Processor (DSP) has been developed to realize a half-rate CODEC for the Personal Digital Cellular (PDC) system. Dual datapath architecture has been employed to execute multiply-accumulate (MAC) operations with a high degree of efficiency. With this architecture. 86.3% of total MAC operations in the Pitch Synchronous Innovation Code Excited Linear Prediction (PSI-CELP) program are executed in parallel, so that total instruction cycles are reduced by 23.1%. The area overhead for the dual datapath architecture is only 3.0% of the total area. Furthermore, in order to reduce power consumption, circuit design techniques are also extensively applied to RAMs. ROMs, and clock circuits, which consume the great majority of power. By reducing the number of precharging bit lines, a power reduction of 49.8% is achieved in RAMs, and above 40% in ROMs. By applying gated clock to clock lines, a power reduction of 5.0% is achieved in the DSP that performs the PSI-CELP algorithm. The DSP is fabricated in 0.5 µm single-poly, double-metal CMOS technology. The PSI-CELP algorithm for the PDC half-rate CODEC can operate at 22.5 MHz instruction frequency and 1.6 V supply voltage. resulting in a low-power consumption of 28 mW.

An embedded cache memory for low power RISC microprocessors is described. An automatic-power-save architecture (APSA) enables the cache memory to operate with high speed at high frequencies, and with low power dissipation at low frequencies. A pulsed word technique (PWT) and an isolated bit line technique (IBLT) reduce the power dissipation of the cache memory effectively. Using these three techniques, the power dissipation of the cache memory is reduced to almost 60% of the conventional cache memory at 60 MHz and to 20% at a clock frequency of 10 MHz. An 8 KByte test chip using 0.5 µm CMOS technology was fabricated, and it achieves 80 MHz operation at a supply voltage of 3.1 V, and 8 mW operation at a supply voltage of 2.5 V at 10 MHz.

A design methodology of high performance deep submicron CMOS in very low voltage operation has been proposed from low power dissipation point of view. In low voltage operation, threshold voltage is restricted by performance, stability of CMOS circuits and power dissipation caused by standby and switching transient current. As a result, threshold voltage is established to be 0.15 V even at 1 V operation from these requirements. Moreover, according to this design, 0.15 µm CMOS was fabricated with reduction of parasitic effects. It achieved propagation delay time 50 psec at 1 V operation. This results confirms that this design methodology is promising to achieve high performance deep submicron CMOS devices for low power dissipation.

Discussed here is reduction of power dissipation for multi-media LSIs. First, both active power dissipation Pat and stand-by power dissipation Pst for both CMOS LSIs and GaAs LSIs are summarized. Then, general technologies for reducing Pat are discussed. Also reviewed are a wide variety of approaches (i.e., parallel and pipeline schemes, Chen's fast DCT algorithms, hierarchical search scheme for motion vectors, etc.) for reduction of Pat. The last part of the paper focuses on reduction of Pst. Reducing both Pat and Pst requires that both throughput and active chip areas be either maintained or improved.

We have proposed a concept of low power drive system for a multi-media TFT-LCD using MFD in which a displayed image is divided into some interlaced subfield images and the number of interlaced subfields can be changed depending on the moving quantities of displayed images. This method has been applied to a 9.5" TFT-LCD and successful operation has been confirmed without moving image degradation.

This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.

Low-power, high-speed match-detection circuits for a content addressable memory(CAM) are proposed and evaluated. The circuits consist a current supply to a match-line, a differential amplifier, and 9-MOSFET CAM cells. The implementation of these circuits made it possible to realize a 16-entry, 32-bit data-compare CAM TEG of 1.2-ns matchdetection time with 5-mW power dissipation in 10-ns cycle-time.

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0.25 µm n-AlGaAs/i-InGaAs HJFET process operates at up to 10 Gbps with power consumption as low as 19 mW at a supply voltage of 1.3 V.